A High - Performance Flexible Architecture

Cryptographic algorithms are more eeciently implemented in custom hardware than in software running on general-purpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to aws discovered in the implemented algorithm or to changes in standards. In this paper we show how reconngurable computing ooers high performance yet exible solutions for cryptographic algorithms. We focus on PipeRench, a reconng-urable fabric that supports implementations which can yield better than custom-hardware performance and yet maintains all the exibility of software based systems. PipeRench is a pipelined reconngurable fabric which virtualizes hardware, enabling large circuits to be run on limited physical hardware. We present implementations for Crypton, IDEA, RC6, and Twoosh on PipeRench and an extension of PipeRench, PipeRench+. We also describe how various proposed AES algorithms could be implemented on PipeRench. PipeRench achieves speedups of between 2x and 12x over conventional processors.